DIGITAL VERIFICATION ENGINEER

CDI

Pavia

10/09/2019

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Référence

2019-9891

Catégorie

Operations — Engineering/production

Secteur Industriel

Autre

Niveau d'études minimum requis

Bac +5 / Master

Niveau d'expérience

3 à 5 ans

Temps de travail

Temps plein

Localisation

Pavia, Lombardia, Italie

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Description

AKKA ranks as the European leader in engineering consulting and R&D services in the mobility sector. As an innovation accelerator for its clients, AKKA supports leading industry players in the automotive,

telco&media, industrial, aerospace, rail and life-sciences sectors throughout the life cycle of their products with cutting edge digital technologies (AI, ADAS, IoT, Big Data, robotics, embedded computing, machine learning, etc.).

Founded 1984, AKKA has a strong entrepreneurial culture and is pursuing fast-paced growth and international development in line with its strategic plan CLEAR 2022. The Group continues to recruit at a steady pace to support its strong business growth. As of 31 December 2018, the Group had 21,019 employees (15,515 at the end of 2017), with 7,879 talents in France (+12.3%), 4,984 in Germany (+5.3%) and 8,156 internationally (+115.5%). Driven by its expertise in future mobility, digital and industry 4.0 technologies, the Group’s 2018 revenue rose by 12.8% to €1,505.3 million and has surpassed the €1.5B cap.

 

With the aim to strengthen our team we are looking for a:

 

DIGITAL VERIFICATION ENGINEER

The resource will be involved in the following activities:

  • Develop test environment, test plan, and test cases based on design specification and verification requirements
  • Work with design team to understand the design intent and bring up the verification plans and schedules
  • Initiate test plan review and verification reviews with the teams at every stage
  • Debug test cases and report verification result to achieve the expected code/functional coverage goal
  • Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
  • Take dedicated ownership to execute block level and SOC level verification
  • Drive the development of behavioral models for analog/MEMS blocks

Profil

Profile

  • MSEE with 5+ years (or PhD with 2+ years) of digital functional verification experience on complex SoC or mixed-signal ASIC product development
  • Proven teamwork skills
  • Excellent analytical and problem solving skills
  • Excellent oral and written communication skills
  • Conversant with some programmable languages such as Verilog, SystemVerilog, Perl/Python/Tcl scripts, Makefile and C++
  • Experienced in Real Number Modeling in SystemVerilog or VerilogAMS language for discrete-time behavioral models of analog blocks
  • Experienced with environment and flow build-up with OVM/UVM/VMM, Metric-Driven verification methodology
  • Experienced with Assertions like PSL or SVA etc
  • Experienced with simulation tools such as VCS or NC-Sim/irun
    (nice to have) Understanding assembly programming and firmware development

Offer

Permanent contract

Location

Pavia

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